1. Field of the Invention
The present invention relates to a variable delay circuit for delaying input data.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a circuit for detecting a frame synchronization used in a communication system using a conventional variable shift register. Referring to FIG. 1A, reference numerals 11-13 each denote a variable shift register, reference numeral 14 denotes a frame synchronization detecting circuit for receiving input or output signals of the variable shift registers 11-13 and detecting a frame synchronization of signals, reference characters S1-S4 denote nodes showing inputs and outputs of each of the variable shift registers 11-13 and the frame synchronization detecting circuit, and reference numeral 15 denotes a bit length setting circuit for providing a delay time for each of the variable shift registers 11-13 and providing a bit length signal to each of the variable shift registers 11-13. In addition, the term "bit length" means the "length of a delay time" in this specification.
FIG. 1B shows received data received by the circuit shown in FIG. 1A. Reference characters DATA0-DATA4 denote data containing necessary information out of those received data and reference characters F1-F4 denote frame synchronization patterns required for detecting a frame synchronization.
An operation is now described. The received data shown in FIG. 1B received by the circuit shown in FIG. 1A is inputted from the node S4 to the variable shift register 13 and then outputted from this circuit through the variable shift register 12 and the variable shift register 11. By appropriately setting the bit length signal applied to the variable shift registers 11-13 in response to a time interval between the frame synchronization patterns F1-F4 involved in the received data, the received data can be delayed by the time interval between the frame synchronization patterns F1-F4 at each of the variable shift registers 11-13. Therefore, at a certain time, the frame synchronization patterns F1, F2, F3 and F4 can be simultaneously detected at the nodes S1, S2, S3 and S4, respectively, by the frame synchronization detecting circuit 14, consequently indicating that the received data has been received in proper synchronization.
FIG. 2 is a block diagram showing a circuit structure of a conventional variable shift register. Referring to FIG. 2, reference numeral 101 denotes a decoder for specifying a register corresponding to an amount of delay by inputting a selected signal of k bits, which corresponds to the bit length signal generating circuit in FIG. 1A, reference characters MUX2-MUXi(i .ltoreq.2.sup.k +1) denote multiplexers which pass an output of a register R1 when they are selected by the decoder 101 and pass an output of a left-hand register when they are not selected, reference characters R2, . . . , Ri denote registers which latch outputs of the above-mentioned multiplexers MUX2, . . . , MUXi and output them to right-hand multiplexers, reference character .phi. denotes a clock signal, reference character DI denotes input data, and reference character DO denotes output data.
The conventional variable register is structured as mentioned above and the decoder 101 receives a selecting signal and specifies one multiplexer out of 2.sup.k multiplexers. When the i-th multiplexer MUXi is specified, only multiplexer MUXi passes the output of the register R1, while other multiplexers pass the outputs of respective left-hand registers. Consequently, the register Ri latches the output of the register R1 in synchronization with the clock signal .phi. and other registers latch the outputs of left-hand registers. When the next clock signal .phi. is entered, the register Ri-1 latches the data of the register Ri and the register Ri latches next data outputted from the register R1. By repeating the above-mentioned operation, the input data DI passes through the register R1 and the register Ri up to the register R2, so that a delay as much as (i+1) clocks is provided and consequently outputted as the output data DO.
Since the conventional shift register is structured as mentioned above, there were problems in which the number of delay stages is limited within the range determined by the number of provided registers. In addition, since the register is used as a memory device, there were other problems in which a large area need be occupied, memory capacity is small and power consumption is increased. Furthermore, there were other problems in which the circuit structure for setting an amount of delay became complicated when a large number of delay stages are required.